? semiconductor components industries, llc, 2011 october, 2011 ? rev. 5 1 publication order number: pacdn006/d pacdn006 6-channel esd protection array product description the pacdn006 is a diode array designed to provide six channels of esd protection for electronic components or subsystems. each channel consists of a pair of diodes that steer an esd current pulse to either the positive (v p ) or negative (v n ) supply. the pacdn006 protects against esd pulses up to: ? ? 8 kv contact discharge, per international standard iec 61000 ? 4 ? 2 ? ? 15 kv per human body model mil ? std ? 883, method 3015 (based on a 100 pf capacitor discharging through a 1.5 k resistor) this device is particularly well ? suited for portable electronics (e.g., cellular phones, pdas, notebook computers) because of its small package footprint, high esd protection level, and low loading capacitance. it is also suitable for protecting video output lines and i/o ports in computers and peripherals and is ideal for a wide range of consumer electronics products. the pacdn006 is available with rohs compliant lead ? free finishing. features ? six channels of esd protection ? ? 8 kv contact, ? 15 kv air esd protection per channel (iec 61000 ? 4 ? 2 standard) ? ? 15 kv of esd protection per channel (hbm) ? low loading capacitance (3 pf typical) ? low leakage current is ideal for battery ? powered devices ? available in miniature 8 ? pin msop and 8 ? pin soic packages ? these devices are pb ? free and are rohs compliant applications ? consumer electronic products ? cellular phones ? pdas ? notebook computers ? desktop pcs ? digital cameras and camcorders ? vga (video) port protection for desktop and portable pcs marking diagram device package shipping ? ordering information http://onsemi.com pacdn006mr msop 8 (pb ? free) 4000/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. 006r = pacdn006mr pacdn 006sm = pacdn006sm 006r msop 8 mr suffix case 846ab electrical schematic 1 234 87 65 v n v p pacdn006sm soic 8 (pb ? free) 2500/tape & reel pacdn 006sm soic 8 sm suffix case 751bd
pacdn006 http://onsemi.com 2 typical application circuit 0.22 f* expansion connector v cc pacdn006 handheld/pda esd protection * decoupling capacitor must be placed as close as possible to pin7. 2 4 5 6 8 1 37 i/o port buffers package / pinout diagrams top view 8 ? pin msop ? 8 v n 1 4 v p ch4 8 5 ch1 006r 27 36 ch2 ch3 ch5 ch6 top view 8 ? pin soic ? 8 v n 1 4 8 5 ch1 pacdn 006sm 27 36 ch2 ch3 v p ch4 ch5 ch6 table 1. pin descriptions pin name type description 1 ch1 i/o esd channel 2 ch2 i/o esd channel 3 v n gnd negative voltage supply rail or ground reference rail 4 ch3 i/o esd channel 5 ch4 i/o esd channel 6 ch5 i/o esd channel 7 v p supply positive voltage supply rail 8 ch6 i/o esd channel
pacdn006 http://onsemi.com 3 specifications table 2. absolute maximum ratings parameter rating units supply voltage (v p ? v n ) 6.0 v diode forward dc current (note 1) 20 ma operating temperature range ? 40 to +85 ? c storage temperature range ? 65 to +150 ? c dc voltage at any channel input (v n ? 0.5) to (v p + 0.5) v package power rating 200 mw stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. only one diode conducting at a time. table 3. standard operating conditions parameter rating units operating temperature range ? 40 to +85 ? c operating supply voltage (v p ? v n ) 0 to 5.5 v table 4. electrical operating characteristics (note 1) symbol parameter conditions min typ max units i p supply current (v p ? v n ) = 5.5 v 10 a v f diode forward voltage i f = 20 ma 0.65 0.95 v i leak channel leakage current ? 0.1 ? 1.0 a c in channel input capacitance @ 1 mhz, v p = 5 v, v n = 0 v, v in = 2.5 v 3 5 pf v esd esd protection peak discharge voltage at any channel input, in system a) human body model, mil ? std ? 883, method 3015 b) contact discharge per iec 61000 ? 4 ? 2 c) air discharge per iec 61000 ? 4 ? 2 (note 2) (note 3) (note 4) (note 4) ? 15 ? 8 ? 15 kv v cl channel clamp voltage positive transients negative transients @ 15 kv esd hbm v p + 13.0 v n ? 13.0 v 1. all parameters specified at t a = 25 ? c unless otherwise noted. v p = 5 v, v n = 0 v unless noted. 2. from i/o pins to v p or v n only. v p bypassed to v n with a 0.22 f ceramic capacitor (see application information for more details). 3. human body model per mil ? std ? 883, method 3015, c discharge = 100 pf, r discharge = 1.5 k ?? v p = 5.0 v, v n grounded. 4. standard iec 61000 ? 4 ? 2 with c discharge = 150 pf, r discharge = 330 , v p = 5.0 v, v n grounded.
pacdn006 http://onsemi.com 4 performance information input capacitance vs. input voltage figure 1. typical variation of c in vs. v in (v p = 5 v, v n = 0 v, 0.1 f chip capacitor between v p and v n ) application information design considerations in order to realize the maximum protection against esd pulses, care must be taken in the pcb layout to minimize parasitic series inductances on the supply/ground rails as well as the signal trace segment between the signal input (typically a connector) and the esd protection device. refer to figure 2, which illustrates an example of a positive esd pulse striking an input channel. the parasitic series inductance back to the power supply is represented by l 1 and l 2 . the voltage v cl on the line being protected is: v cl fwd voltage drop of d 1 v supply l 1 d ( i esd ) dt l 2 d ( i esd ) dt where i esd is the esd current pulse, and v supply is the positive supply voltage. an esd current pulse can rise from zero to its peak value in a very short time. as an example, a level 4 contact discharge per the iec61000 ? 4 ? 2 standard results in a current pulse that rises from zero to 30 amps in 1 ns. here d(i esd )/dt can be approximated by i esd / t, or 30/(1x10 ? 9 ). so just 10 nh of series inductance (l 1 and l 2 combined) will lead to a 300 v increment in v cl ! similarly for negative esd pulses, parasitic series inductance from the v n pin to the ground rail will lead to drastically increased negative voltage on the line being protected. another consideration is the output impedance of the power supply for fast transient currents. most power supplies exhibit a much higher output impedance to fast transient current spikes. in the v cl equation above, the v supply term, in reality, is given by (v dc + i esd x r out ), where v dc and r out are the nominal supply dc output voltage and ef fective output impedance of the power supply respectively. as an example, a r out of 1 would result in a 10 v increment in v cl for a peak i esd of 10 a. if the inductances and resistance described above are close to zero, the rail ? clamp esd protection diodes will do a good job of protection. however, since this is not possible in practical situations, a bypass capacitor must be used to absorb the very high frequency esd energy. so for any brand of rail ? clamp esd protection diodes, a bypass capacitor should be connected between the v p pin of the diodes and the ground plane (v n pin of the diodes) as shown in the application circuit diagram below. a value of 0.22 f is adequate for iec ? 61000 ? 4 ? 2 level 4 contact discharge protection ( ? 8 kv). ceramic chip capacitors mounted with short printed circuit board traces are good choices for this application. electrolytic capacitors should be avoided as they hav e poor high frequency characteristics. for extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate
pacdn006 http://onsemi.com 5 the effects of the parasitic series inductance inherent in the capacitor. the breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. as a general rule, the esd protection array should be located as close as possible to the point of entry of expected electrostatic discharges. the power supply bypass capacitor mentioned above should be as close to the v p pin of the protection array as possible, with minimum pcb trace lengths to the power supply, ground planes and between the signal input and the esd device to minimize stray series inductance. additional information see also on semiconductor application notes ap209, ?design considerations for esd protection? and ap219, ?esd protection for usb 2.0 systems?. ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? positive supply rail channel input ground rail chassis ground system or circuitry being protected line being protected one channel of pacdn006 d 2 d 1 l 1 l 2 v cl v n v p 0.22 f path of esd current pulse i esd 0 a 20 a figure 2. application of positive esd pulse between input channel and ground
pacdn006 http://onsemi.com 6 package dimensions msop8 case 846ab ? 01 issue o s b m 0.08 (0.003) a s t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. 846a-01 obsolete, new standard 846a-02. b e pin 1 id 8 pl 0.038 (0.0015) ? t ? seating plane a a1 c l *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 8x 8x 6x mm inches scale 8:1 1.04 0.041 0.38 0.015 5.28 0.208 4.24 0.167 3.20 0.126 0.65 0.0256 dim a min nom max min millimeters ?? ?? 1.10 ?? inches a1 0.05 0.08 0.15 0.002 b 0.25 0.33 0.40 0.010 c 0.13 0.18 0.23 0.005 d 2.90 3.00 3.10 0.114 e 2.90 3.00 3.10 0.114 e 0.65 bsc l 0.40 0.55 0.70 0.016 ?? 0.043 0.003 0.006 0.013 0.016 0.007 0.009 0.118 0.122 0.118 0.122 0.026 bsc 0.021 0.028 nom max 4.75 4.90 5.05 0.187 0.193 0.199 h e h e d d e
pacdn006 http://onsemi.com 7 package dimensions soic 8, 150 mils case 751bd ? 01 issue o e1 e a a1 h l c e b d pin # 1 identification top view side view end view notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. symbol min nom max a a1 b c d e e1 e h 0o 8o 0.10 0.33 0.19 0.25 4.80 5.80 3.80 1.27 bsc 1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 l 0.40 1.27 1.35 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 pacdn006/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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